1. Field of the Invention
The present invention relates to a semiconductor device and a connection checking method for a semiconductor device. The present invention relates particularly to a semiconductor device and a connection checking method for a semiconductor device which make it possible to check on a connection between a land and a connection terminal connected to the land.
2. Description of Related Art
In a package on package (POP) structure, as shown in FIG. 4, a first land 210 is formed in the top surface of a package substrate placed in the lower tier of the structure. Solder balls 40 formed on the undersurface of a multi-chip package (MCP) 4, such as a memory, placed in the upper tier of the structure are connected to the first land 210 (see FIG. 1). The first land 210 is connected to a second land 211 formed in the undersurface of the package substrate 2 through a connection interconnection 212. Solder balls 213 are connected to the second land 211. It is important to properly connect the second land 211 and the solder balls 213 so that a favorable electric connection between the solder balls 213 and the MCP 4 can be secured.
Meanwhile, semiconductor device manufacturers/shippers, for instance, purchase package substrates, manufacture semiconductor devices by forming semiconductor chips and solder balls on the package substrates, and subsequently ship the semiconductor devices. The semiconductor device manufacturers/shippers are required to guarantee a proper connection between the solders ball in question and the second land.
To this end, the semiconductor device manufacturer/shippers check on the connection between the second land 211 and the solder balls 213. Note that solder balls 203 connected to the semiconductor chip 3 through connection interconnections 202 are also formed in the undersurface of the package substrate 2 so as to be connected to a semiconductor chip 3. The electrical connection between these solder balls 203 and the semiconductor chip 3 can be checked on by use of the semiconductor chip 3.
Whether or not the solder balls 213 not connected to the semiconductor chip 3 are connected to the second land 211 properly is checked as shown in FIG. 4, for instance. To put it specifically, a connection checking apparatus 100 includes an upper socket 110 and a lower socket 120. The upper socket 110 includes measurement pins 111. The lower socket 120 also includes measurement pins 121. By use of the connection checking apparatus 110 of this type, a semiconductor device a is inserted between the upper socket 110 and the lower socket 120. Subsequently, the measurement pins 111 of the upper socket 110 are positioned to the first land 210 of the semiconductor device a, whereas the measurement pins 121 of the lower socket 120 are positioned to the solder balls 213 of the semiconductor device a. Thereafter, the semiconductor device a is sandwiched between the upper socket 110 and the lower socket 120. Thus, the measurement pins 111 of the upper socket 110 and the measurement pins 121 of the lower socket 120 are respectively brought into contact with the first land 210 of the semiconductor device a and the solder balls 213 at a time. Afterward, a voltage or an electric current is applied to the measurement pins 111 or the measurement pins 121, and a value of the resistance between the first land 210 and each solder ball 213 is thus measured. When the resistance value is smaller than a predetermined threshold value, it can be confirmed that the first land 210 is connected to the solder balls 213 properly. On the contrary, when the resistance value is equal to or larger than the predetermined threshold value, it can be confirmed that the first land 210 is connected to the solder balls 213 defectively. As described above, when the proper connection between the first land 210 and the solder ball 213 can be confirmed, the proper connection between the second land 211 and the solder balls 213 can be guaranteed.
For reference, Japanese Patent Application No. 2008-232769 discloses a method of judging a proper connection in a semiconductor device having the POP structure.
The semiconductor device a having the configuration shown in FIG. 4 has the following problems in checking on the connection between the second land 211 and the solder ball 213.
To put it specifically, the measurement pins 111 of the upper socket 110 need to be positioned to the first land 210 of the semiconductor device a, and the measurement pins 121 of the lower socket 120 need to be positioned to the solder balls 213 of the semiconductor device a. During their positioning, if the upper socket 110 is positioned to the semiconductor device a with poor accuracy as shown in FIG. 5, an area around the first land 210 in the package substrate 2 is likely to be damaged.
Furthermore, in a case where the measurement is carried out multiple times for some reason such as a poor electrical connection between the first land 210 and the measurement pins 111, the front extremity portion of the measurement pins 111 contacts the first land 210 multiple times. This might cause damage to the first land 210.